`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/10/20 09:56:19
// Design Name: 
// Module Name: gpio_intr
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module gpio_intr(
    input       clk,
    input       rst_n,

    input          trigger,
    input          acq_done,
    input          ff_empty,
    input          axi_busy,
    output reg         gpio_intr,
    output reg [2:0]   state
    );
localparam  IDLE      = 3'd0;
localparam  AC_WAIT   = 3'd1;
localparam  FF_WAIT   = 3'd2;
localparam  AXI_WAIT  = 3'd3;
localparam  DONE      = 3'd4;

reg [2:0]   next_state;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        state <= IDLE;
    end else begin
        state <= next_state;
    end
end

always @(*) begin
    case (state)
        IDLE: begin
            if (trigger) begin
                next_state = AC_WAIT;
            end else begin
                next_state = IDLE;
            end
        end
        AC_WAIT: begin
            if (acq_done) begin
                next_state = FF_WAIT;
            end else begin
                next_state = AC_WAIT;
            end
        end
        FF_WAIT: begin
            if (ff_empty) begin
                next_state = AXI_WAIT;
            end else begin
                next_state = FF_WAIT;
            end
        end
        AXI_WAIT: begin
            if (!axi_busy) begin
                next_state = DONE;
            end else begin
                next_state = AXI_WAIT;
            end
        end
        DONE: begin
            next_state = IDLE;
        end
        default: next_state = IDLE;
    endcase
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        gpio_intr <= 0;
    end else begin
        case (state)
            IDLE:       gpio_intr <= 0;
            AC_WAIT:    gpio_intr <= 0;
            FF_WAIT:    gpio_intr <= 0;
            AXI_WAIT:   gpio_intr <= 0;
            DONE:       gpio_intr <= 1;
        endcase
    end
end

endmodule
